While there have been some attempts to protect internal circuits from destruction, these attempts have not been entirely successful.
FIGS. 10A and 10B entirely and partially illustrate GND (ground) and power supply pads mounted on a conventional semiconductor apparatus 46 formed from a P-type semiconductor substrate 3. As shown in FIG. 10A, an inner core region 5 is formed at a central portion of the semiconductor apparatus 46. An inner circuit formed from a plurality of semiconductor elements is located in the inner core region 5. A plurality of pad areas 7 is also formed in an outer region 15 of the semiconductor apparatus 46. An I/O cell 47 is provided per pad area 7 on the semiconductor substrate 3 between the inner core region 5 and pad area 7. There are provided an inner core region use Vcc line 11a and an inner core region use GND (ground) line 11b, each formed from a metal wiring layer, between the inner core region 5 and I/O cell 47. Lines 11a and 11b continuously circumscribe the inner core region 5. Further, to continuously extend over a plurality of I/O cells 47, an I/O cell use Vcc line 49a and an I/O cell use GND line 49b, each formed from a metal wiring layer, are provided.
As shown in FIG. 10B, the inner core region use Vcc line 11a and I/O cell use Vcc line 49a are electrically connected to a metal wiring layer 51a which is electrically connected to an electric power supply use pad area 7a through via holes 11c and 49c. The inner core region use GND line 11b and I/O cell use GND line 49b are electrically connected to the metal wiring layer 51b which is electrically connected to a GND use pad area 7b through via holes 11d and 49d. The inner core region use Vcc line 11a is electrically connected to a metal wiring layer 53a extending over in the side of inner core region 5 through a via hole 11e. The inner core region use GND line 11b is electrically connected to a metal wiring layer 53b extending over to the side of inner core region 5 through a via hole 11f. 
FIG. 11 illustrates an exemplary configuration of a conventional pad area 7 and I/O cell 47. FIG. 12 illustrates an equivalent circuit thereof. Each I/O cell 47 is configured from a protection circuit and input buffer 17. The protection circuit is configured from a P-channel type MOSFET (Metal Oxide Silicon Field Effect Transistor) Tr5 (herein after referred to as a MOS transistor Tr5), a N-channel type MOS transistor Tr6, and a resister R (not shown).
As shown in FIG. 11, the MOSFET transistor Tr5 is formed in a P channel region of a N-well formed on the P-type semiconductor substrate. A gate electrode is configured from a polysilicon electrode 55. An area required for forming the MOS transistor Tr5 is approximately 1800 μm. The MOS transistor Tr6 is formed in an N-channel region of a P-type semiconductor substrate. Both source and drain of the MOS transistor Tr6 are configured from a N-type impurity diffusion layer (N-type impurity) formed on the P-type semiconductor substrate. A gate electrode is configured from a polysilicon electrode 57. An area required for forming the MOS transistor Tr6 is approximately 1000 μm.
As depicted in FIG. 12, both the poly-silicon gate electrode 55 and a source of the MOS transistor Tr5 are connected to power supply “Vcc”. Respective drains of the MOS transistors Tr5 and Tr6 are connected to each other, and further connected to the pad area 7. Both the poly-silicon gate electrode 57 and source of the MOS transistor Tr6 are connected to ground “GND”. One end of the resistance is connected to a connection point connecting drains of the MOS transistors Tr5 and Tr6.
As further shown in FIGS. 11 and 12, the input buffer 17 is configured from an inverter circuit formed from P-channel type and N-channel type MOS transistors Tr3 and Tr4. The MOS transistor Tr3 is formed in the P-channel region of the N-well formed on the P-type semiconductor substrate. Both the source and drain of the MOS transistor Tr3 are configured from P-type impurity diffusion layers formed in the N-well. A gate electrode is configured from a polysilicon electrode 59. The MOS transistor Tr4 is formed in an N-channel region of the P-type semiconductor substrate. Both the source and drain of the MOS transistor Tr4 are configured from N-type impurity diffusion layers (N-type impurity) formed on a P-type semiconductor substrate. A gate electrode is configured from a polysilicon electrode 61, as shown in FIG. 11.
As depicted in FIG. 12, the source of the MOS transistor Tr3 is connected to the power supply “Vcc”. The source of the MOS transistor Tr4 is connected to ground (GND). Respective drains of the MOS transistors Tr3 and Tr4 are connected to each other, and are lead to the inner core region 5. Respective polysilicon gates 59 and 61 of the MOS transistors Tr3 and Tr4 are connected to each other, and further connected to the other end of the resistance.
As illustrated in FIGS. 10 to 12, none of the circuits are conventionally formed on the pad area 7 of the semiconductor substrate 3. That is, punching through phenomenon occurs in a metal wiring layer forming the pad area 7 when wire-bonding is performed with a bonding wire so as to electrically connect the pad area 7 to an external terminal during an assembling process for the semiconductor apparatus. As a countermeasure, a well or the like is formed in the range of the pad area 7 on the semiconductor substrate 3.
Further, based upon recent miniaturization, downsizing (i.e., shrinkage) is promoted in order to decrease cost for a semiconductor product. For the purpose of avoiding destruction of an internal circuit caused by a voltage excessively input from a pad, a protection circuit for an I/O cell is typically provided.
However, since a withstand pressure of a MOS transistor simply decreases in accordance with the miniaturization, and an area occupied by the protection circuit cannot be minimized, the protection circuit prevents the shrinkage.
Further, in accordance with the miniaturization, the inner core region is downsized, and accordingly, the I/O cell increases a rate of its occupation in a semiconductor apparatus. Thus, when shrinkage is promoted, there are pressing needs to minimize the area occupied by the I/O cell in the semiconductor apparatus. Further, as illustrated in FIG. 11, a rate of an area for a pad area 7 is high.
However, since multiple layers, formed from inter-laminar insulation layers and metal wiring layers, are formed between a surface of a pad and a semiconductor substrate by a recent multiple layer technology of metal wiring layers, damage to the semiconductor substrate, caused by the wire bonding in the pad area, does not prominently occur in comparison with that in the past. In addition, even formation of a well is needless nowadays. Despite that, semiconductor apparatus used in the past generally are configured to form none of the semiconductor elements within a pad area.
As a conventional technology that efficiently utilizes a pad area, Japanese patent application Laid Open No. 2000-12778 discloses one example. Specifically, a protection circuit is formed on an N-type semiconductor substrate, having an NPN configuration. The protection circuit is formed from an N-implant diffusion layer, a P-type island region including a P-implant layer and P-diffusion layer, and a N-diffusion layer formed on the island region.
However, when the protection circuit, disclosed in Japanese patent application Laid Open No. 2000-12778, is formed, both N and P-type implant layers are necessitated. As a result, a problem of increasing a number of manufacturing processes occurs when such a manner is applied to a semiconductor apparatus excluding an implant layer.